11/20, 11/15 born. Small Scale integration. 4 or 8k words mem,
28k max. (Some documentation referred to 32k max memory, but the
top 4k was reserved for the I/O space. Machines with 28 KW core
were rare, and most were shipped with 4 KW or 8 KW). Magnetic
Core Memory. TTY ASR33 console. Papertape reader/punch typical
I/O. Clock State cpu control. [All subsequent PDP-11 machines
were to be microcoded]. The processor boards, all 15 of them
(plus an optional line time clock, KW11-A), plugged into a 3 bank
4 x 6 slot backplane. Each 4 KW of memory occupied a further 4 x
6 slot backplane with some 12 modules. There was room in the 11"
CPU drawer for three such additional backplanes. The MM11-E 4 KW
memory module took 1.2us for a full memory cycle.
Q: Why does the 11/20 have 18 bit addresses on the UNIBUS but only a
CPU capable of handling 16 address bits?
A: Because it was always intended to provide an MMU option to
allow for extended addressing.
No matter what memory configurations, 16 bit, 18 bit or 22
bit were to be employed throughout the life of the PDP-11 family,
the top 8 KB were always reserved for I/O addresses, registers, etc.
In particular (initial list provided by Megan Gentry):
The I/O page is 8 KB standard
Some systems (PDT) have 4 KB I/O pages
Some systems can be configured for 4 KB I/O pages
There is a quirk in the memory management units
which cause the microcode to assume an 8 KB I/O page
regardless of the jumper configuration - so, if you have a
system configured for a 4 KB I/O page and turn on the memory
management unit, the system will suddenly think it has an 8 KB
I/O page. This can cause, for example, RT-11XM to go south
really quickly. A possibly-related feature is that, after
reset, the memory map has kernel memory corresponding to low
physical addresses for the first seven segments, and the last
segment pointing at -8KB. This was to allow
bootstrap programs to easily access device registers without
needing to know about memory management.
The address of the I/O page (8 KB) is, on 16-bit systems,
160000. On 18-bit systems, 760000. And on 22-bit systems,
11/45. This was the first of the highspeed processors that begat
11/50, 11/55 and 11/70. 11/45 was microcoded, SSI/MSI, memory
bus, core, MOS or bipolar memory. Max Memory 256 KB addressable
via optional 18 bit Memory management unit. Optional Floating
Point Unit. 11/55 had special bipolar high speed mem. Fast
peripheral to memory slots Split I&D spaces. Introduced some
extra instructions such as MUL, DIV, ASH, ASHC, SPL. The 11/45,
/50 and /55 had the same CPU - the differences being in memory
types, bus layouts, etc. The 11/70 was to have essentially the
same cpu, with modifications to allow for Cache, 22-bit
addressing and, for the first time, non-Unibus memory.
The PDP-11/45/50/55 had two Unibuses, normally joined by a single
spaced jumper. The second Unibus has no arbitration, and was part
of dual-ported fastbus memory. If you had fastbus memory (which
made a 45 a 50 or 55), a second processor could access the
memory. The only problem was that with the Unibus A and B split,
DMA devices on Unibus A could not see the fastbus memory. I [not
MMcC] had a PDP11/50 and PDP11/20 set up in such a fashion, with
the PDP11/20 doing high speed A/D sampling and signal averaging
using shared memory with the PDP11/50.
The fastbus memory is an independent high speed data bus internal
to the 11/45 xx processors, with up to two solid state memory
controllers and had each controller had two ports one for the CPU
and the other available for a second Unibus where concievably a
high speed DMA device could directly write to the memory. The DMA
device on the `second' bus had to have a Unibus priority
arbitration system, so you could in fact connect another CPU to
it a bit like the DTS07's in concept. Note that, just to confuse
the issue, this is not the same as the product/feature later
marketed as FASTBUS.
KB-11 was the original /45 cpu, and used the FP-11 asynchronous
FPP. Later machines under the /45 label were core memory /55s.
11/40, 11/35. Price same as 11/20, higher performance. (See
tables and chart below for relative performance of the various
PDP-11 processors) Small- and Medium-Scale Integration.
Architecture of CPU like 11/45 without the raw power. Memory
Management Unit, EIS/FIS Extended and Floating instruction sets
as options. Introduced with Core memory, and later with MOS.
Microcoded. Max Memory 256 KB. Extra instructions such as SOB XOR
MARK SXT and RTT introduced. MUL, DIV etc implemented in the EIS
11/05, 11/10. Performance same as 11/20, lower price.
Microcoded. 2-board processor. New 8 KW 3-board core memories
were introduced with the /05 and /40. Later on, 16 KW memories
were used before core got supplanted my MOS Memory. I remember
these memories spec'd for a 980ns read/write cycle. I also
remember the 11/05 CPU boards having the most green ECO wires I
had ever seen on a machine. The cost of adding those wires
manually must have, on reflection, added significantly to the
cost of manufacture of the 11/05. Later board revisions
eliminated these almost completely. It is interesting to
consider that modern design, simulation and testing tools has
virtually eliminated the ECO wire practice - a practice that we
took for granted during the '70s and early '80s.
The /05 front panel has the following control switches:
LOAD ADRS EXAM CONT ENABLE/ START DEP HALT
When HALTed, the CONTinue key performed a single instruction per
key depression (as do all the other 11's with front panels.)
There is a single 16 bit ADDR/DATA multiplexed display and a
single RUN status light. The power switch has the following
positions : OFF / POWER / PANEL LOCK.
11/70. CPU very similar to 11/45 in raw performance. Machine
introduced with had core initially and MOS later. These machines
introduced Cache, 22-bit Memory management of up to 4
MB. Optional Floating point processors. Massbus periperal
controllers which had a direct path to memory first appeared on
this machine. Note that MASSBUS (RH70's) adapters attached
directly to memory were unique to the 11/70 -- MBAs only
otherwise appeared on different series (PDP-10, VAX etc). Unibus
systems could use MASSBUS peripherals, but the controllers
(RH11's) spoke over the Unibus and lost most of the speed
advantage. While this machine was not the fastest -11 (that title
belongs to the bipolar memory equipped 11/55), no other -11 could
approach the 11/70 in terms of I/O throughput over its multiple
massbus/memory bus architecture.
The KB-11B was the original 70 cpu. Similar to the KB11 based
11/45, plus unbus map, 22-bit, MBCs etc. The 11/70 had the
`feature' of the slowest bus of ANY -11. And when a UNIBUS
peripheral did DMA, EVERYTHING stopped! This is one of
the reasons the Seti upgrades are so good. They enable the RHs,
CPU, and UNIBUS to all operate in parellel.
KB-11C: The FP-11 proved `featureful' in practice, and was
replaced with a faster synchronous FP-11C. This required the
`FP-11C compatible KB-11.'
The 11/70 was a 18 month overnight wonder to fill the gap left by
the late development of the 32-bit wonder box! :-)
The C/D cpus used the FP-11C FPP. In fact, the KB-11C is referred
to as the `FP-11C compatible KB-11' in some manuals.
Relative CPU performance: 0.60 (VAX780 = 1.0)
Technology: SSI/MSI TTL
I/O Bus Capacity: 4 MASSBUS ports
Space Requirements: 9.0 square feet (2 H960)
Power Requirements: 6,000W
LSI-11, first of the microprocessor -11s, implemented on 4
chips. It was sold by Western Digital as the WDC-16.
First of the Q-bus machines (All others above were UNIBUS).
Implemented on a single quad height board. Performance
approximately equalled that of the 11/05. Minimal size. Aimed at
OEM embedded controllers, etc.
11/03 Same microprocessor as 11/2. Performance the same as the
11/05, but priced much less. Qbus. More expandable than
LSI-11/2. Aimed at low end of 11/05 market.
11/04. UNIBUS. There are conflicting reports about this model.
One is that it was a replacement for the 11/05, with the same
performance, but priced much less. Standard TTL and STTL logic.
It only used one cpu board instead of the 11/05's two. The other
version is that it was a "reduced" version of the 11/34, with 16-bit
addressing, no cache, no FPP option, etc. It was designed by the same
person as the /34, and it fitted on one UNIBUS board. Apparently
introduced in 1978?
11/34. Follow-on to 11/40 with same performance at lower
cost. Two board cpu in SSI/MSI TTL. Initially had a two-switch
KY11-LA front panel (Halt&Boot). Optional calculator-style Octal
KY11-LB front panel later, although most customers opted to have
this as time progressed. The KY11-LB could be used to singlestep
or microstep a program for diagnostic use. The /34 style memory
managment was 18 bit and the memory management was standard.
11/55 had special high speed (300 ns) bipolar mem. Floating point
as option. Dual register set, as well as Kernel, Supervisor and
User CPU operating modes as on the 11/45, 11/50, and (later)
11/70. Interestingly, a table in Bell/Mudge/McNamara's Computer
Engineering (page 406) shows the 11/55 performance relative to
the 11/03 for basic instructions per second as 41 (vs 36 for the
/70) and Whetstones of 725 (vs 671 for the /70). Obviously the
300 ns bipolar memory made a difference in raw performance. Of
course this system could not approach the /70 in throughput.
KB-11D The 18 bit version of the C. used in /55s and very late
/45s. I think all /50s were KB-11 cpu's. (PaulR)
The big difference between a /50 and a /55 is the /55 is a KB-11D,
not a KB-11 cpu:
KB-11: 11/45, 11/50
KB-11E: 11/74* that never shipped.
* See the section.
LSI-11/2 (11/21?) KD11-HA. Double height module follow-on to
LSI-11. Performance of an 11/05, but priced much less. Qbus.
Lacks onboard memory and WCS chip socket. Basically the same
chipset. Both used in PDP-11/03 systems. LSI-11 sucks more
power than the LSI-11/2.
The LSI-11/2 chipset was simply "the LSI-11 chipset,"
manufactured by WDC for DEC. FIS/EIS upgrade microms (MICrocode
ROMS) were available for the LSI-11, and at least on the PDT-11s
there was a special 2-in-1 version of the regular CPU microms
that would free up a socket for the FIS/EIS microm.
11/60. Intended follow-on to 11/40 at the high end/same
price. Higher performance. Writable control store for custom
instructions. Cache and ECC MOS memory. Too costly, too late.
Memory management was 18 bit and standard. Floating point
instructions were standard - but implemented by the CPU
microcode. There was a floating point coprocessor option. The 60
was to have been a 22 bitter originally.
11/34a, 11/34c. The /34a with the "right cache" presented a
higher level of performance than the then "hot machine" of the
time - I believe it was the /60 - in the eyes of -11 engineering /
central engineering. The "c" upgrade was the re-establishment
of the original cache. Thus, the /34c was an internal mythical
model to allow FS to keep track of what systems had the upgrade -
much like the /35 vs /40 clock mod that made the /35 faster.
PDT family. PDT 11/110, 11/130, 11/150.
The PDT-11/110 and -11/130 were built into the cardcage of a
VT100 (along with the terminal). The 11/110 simply had code to
allow down-loading of the PDP-11. It had no peripherals. The
11/130 had two TU58's mounted just under the monitor. The
PDT-11/150 was built into a table-top unit which also had two
RX01 equivalent drives, and the cpu board was built into the the
Floppy box. The PDT-150 had separate VT100 and systems box. The
system box for the single disk unit: 51.0 cm (20.08 in) length X
33.02 cm (13.0) width X 20.9 cm (8.23 in) height and 33 pounds.
Dual disk unit: same, but 34.8 cm (13.42 in) height and 46
pounds. The box slopes to the front and has a small front panel
that reads `digital PDT-11' and has four LEDs ("1", "2", "RUN",
"POWER"). LED 1 Lights to indicate a system error when in the
self-test mode. LED 2 lights to indicate that the system is
waiting for an autobaud response from the console terminal.
Otherwise both can be controlled by a user program. The top of
the case is plastic and is held fast by two screws; undoing these
allows access to the CPU and logic. Two RX01 drives (8.5"
floppies) are mounted in the bottom 75% of the cabinet. There
are three terminal ports, one console port, one printer port, and
one modem port. The 3 terminal ports are optional. All of the
connectors, save for the modem port, are female DB25 connectors,
which I have been told is rare. Depending upon the version of
RT-11 being used, the machine expects either VT52 or VT100
console/terminal input -- I believe that versions prior to 4.0
default to VT52. The stock memory appears to be about 30K words
(not including the I/O page). It is also noteworthy that the
RX01 firmware is suspected of not being strictly "real" RX01.
The PDT will write fresh single-density formatting every time it
writes to the disk. It's also interesting to note that the
physical device name for the drives is PD: instead of DX: The
documentation calls the drive controller an RXT-11. It also
claims that a PDP11/V03 with RXV11 is compatible with the
PDT11/150. The print set shows 27 sectors/track for the PDT.
The RX02 User's Guide shows 26 sec./trk.
All three PDT's had the equivalent of an 11/2 (same chip set, in
fact) and 60 KB addressable (rather than 56 KB, since it had only a
4 KB I/O page) These machines, running RT11, could be viewed as
being the forerunners of today's PCs. They were never marketed as
such, and thus faded into obscurity. Although there is no I/O bus,
per se, the print set gives the controller card equivalent for the
11/44. Successful follow-on to 11/40 high end/11/70 low end.
Almost 11/70 power at 11/40 price. UNIBUS. Also, it could have
the CIS option. The front-end processor on this system was built
around the Intel 8085. Lacked the dual register set of the 11/70.
Relative CPU performance: 0.42 (VAX780 = 1.0)
Technology: SCHOTTKY TTL MSI
Maximum memory: 4 MB ECC MOS
Maximum I/O throughput: 5 MB/s UNIBUS
Cache size: 8 KB
Cache Cycle time: 275 ns
Space requirements: 4.4 square feet (H9642)
Space requirements: 6.3 square feet (H9645)
Power requirements: 1,224W
11/23. Successful follow-on to 11/03. Single F(onz)-11 chip.
11/34-ish performance at lower cost. Qbus. F11 chip does 22 bit
addressing, but only 18 address lines brought out in earliest
versions; all 22 brought out on later revs of the KDF11-A.
11/24. successful follow-on to 11/04, 11/34. F-11 (Fonz) chip. Price of
11/04, performance of 11/34. The 11/23 and /24 had the 11/34
style memory management. They both had 22 bit addressing, but
for the /24, the UNIBUS map (to map 18-bit UNIBUS DMA addresses
onto the 22 bit memory address) was a (rather rare) option
called, I believe, a KT24.
The T-11 (Tiny) is a similar architecture to the LSI-11 on a
single 40-pin DIP that was primarily intended for the embedded
market. It was used only in the Falcon SBC-11/21 and a few
controllers (e.g. RQDX3, DEUNA, LA-120). The T-11 was also used
in the KXT11-CA Quad width `communications processors' that
allowed you to have multiple CPU's on the Qbus. One cancelled
DEC project used it as a cpu/controller inside a telephone (with
keyboard, video, etc).
PRO-350, PRO-325. This machine was released as one of a
triumvirate of PCs by DEC. The PCs consisted of the DECmate-II
PDP-8/WPS based dedicated word processor; the 8080/8086 based
Rainbow, and the F-11 based PRO-325/350. Although the machines
were well engineered, they were not successful in the marketplace
for a number of reasons. First, the customer base was confused
by being offered three totally separate, incompatible
offerings. Second, the Rainbow, although able to run both CP/M
and MS/DOS, was incompatible in both hardware and software with
the IBM PC that was establishing the defacto standards for the
industry. And third, the PRO-350 was based on a bounded,
restricted version of RSX11, and was viewed as an oddity in the
The PRO-325 was the same as a PRO-350, but it only had the RX50's
in it; the PRO-350 also had an RD-series hard drive (originally
an RD50, but with newer controllers you could have up to an
RD52). The PRO-380 was the same as the PRO-350 with respect to
devices. All three had a bitmap display. The PRO-325/350 was
based on the F-11 (11/23) chip set. The PRO-380 was based on the
J-11 (Jaws, 11/73) chip. They all were desktop units, though an option
allowed them to be mounted in a tower configuration.
Note on the Pro 380: one reason for its failure was its bad
performance. It ran the J-11 at only 10 MHz. Reason was a design
mistake: the entire system has only one clock, 20 MHz, for everything
from CPU to video to UART baud rates. J-11 was planned to do 20 MHz,
fab only got it to 18, but the design didn't allow for a separate CPU
clock so the Pro had to go all the way down to 10.
PRO-380. This was an upgrade to the PRO-350, using the J-11
chipset. The market opportunity was closed to it at this time,
and they only had limited success. The PRO-350/380 probably saw
most use as console devices/frontends for a number of the VAX8000
In the following sections, quotes marked [-PSH] are extracts from the
1987 "PDP-11 Systems Handbook"
11/73, Follow-on to 11/23, 11/24. J(aws)-11 chip. Similar cost,
higher performance. Replacement for 11/44.
The MicroPDP-11/73 computer provides one-third more compute
power than the MicroPDP-11/53, ... 15-megahertz J-11 chip ...
Memory is expandable in 1- and 2-Mbyte increments ....
11/73 is the KDJ11-A or KDJ11-B. (The -B just puts things like
the console SLU and boot roms onto one board; some revs also have
PMI memory ... the boundary between the 11/73 and 11/83 is a bit
fuzzy...). There was never a UNIBUS equivalent of the /73. The
/73 didn't replace either the /44 or the /70. (Nothing
replaced the 11/70! Nothing else had the I/O throughput, and the
CPU was only just outrun by the 11/83 / 11/84.)
11/83, 11/84 Higher performance versions of 11/73.
The computing power of the MicroPDP-11/83 has twice the
performance of the MicroPDP-11/73 .... The MicroPDP-11/83, by
combining an 18-megahertz J-11 chip and a companion
floating-point accelerator chip with a new private memory
interconnect on one module, .... [-PSH].
The MicroPDP-11s (11/23+, /73 and /83) were in a tower
configuration which could be configured for desktop use, or the
innards removed and rack-mounted. (The differences between the
/73 and the /83 were simply:
The board clock speed, 15 MHz vs 18 MHz (some /83s ran at
the type of memory. The 11/83 had PMI memory which was
configured before it on the Qbus.
The 11/8x can't go much above 18 MHz. While the original design
called for 20 MHz, neither the J11's nor the gate arrays were up
to it. They use Private Memory Interconnect (PMI) much like the
11/70 did years earlier. The memory (for the /83) lives in the
usual PMI slots, and then a bus adapter brings the bus out to the
UNIBUS. DEC realized that they had a lot of customers with
UNIBUS peripherals, but they didn't want to build another UNIBUS
processor (the previous one being the 11/24), so they expanded on
the 11/24 + KT-24 concept and came up with the 11/84. It was mostly
UNIBUS, but the first slots were QBUS (so it could use the KDJ11-B
boards used in the 11/83), followed by a QBUS-UNIBUS adaptor.
Considering that at that time, all DEC had on the Qbus was the
RD-series and the KDA50 which started out as a real power pig,
UNIBUS was the way to go if you wanted a system with big (but
genuine DEC) disks and high-end tapes.
An alternate viewpoint from Don Stokes:
I'm not sure I agree re the peripherals for the 11/8x and
onward. The KDA50 was a pig, but so was the UDA50, and by
then DEC weren't selling anything but RAxx drives as "big"
disks. Tapes were always a problem, but the TU81 was
available by the mid 80s, and the TS05 was also available. I
got the distinct feeling that the 11/84 was aimed at upgrades
and additions for sites with a heavy UNIBUS investment rather
than for new systems/sites. After all, burst mode made the
Qbus faster than the UNIBUS, the boxes were smaller and much
less power hungry. (KDA50 notwithstanding -- KDA50s
inevitably got put in an expansion chassis because of the
power. But at least the expansion box could hold 5.25" drives
I never could understand why DEC abandoned dedicated
peripheral controllers in favour of the UDA50. We used to get
much more throughput (commercial loads) out of 11/70s with
RP06s and RM05s than we ever could with RA81/UDA50 equipped
11/750s running the same applications. 11/44s seemed
Relative CPU performance: 0.72 (VAX780 = 1.0)
Technology: J-11 18 MHz Chipset MSI/LSI
Maximum memory: 4 MB PMI ECC MOS
Bus Capacity: 5 MB/s UNIBUS
FPA standard, FPP standard
Cache: 8 KB
Space Requirements: 6.2 square feet (H9642)
Power Requirements: 1,100W
11/53. Essentially a stripped down /73. KDJ11-D I think -- J11
chip, 15MHz, lacked cache or FPA options, has (slowish) onboard
memory. There wasn't a /54.
The heart of the MicroPDP-11/53 is a 15-megahertz, J-11
single board computer with 0.5 Mbytes of onboard memory ...
The MicroPDP-11/53 PLUS supermicrosystem ... has an
additional 1 Mbyte of memory for a total of 1.5 Mbytes of
onboard memory. [-PSH]
11/93, 11/94 Possibly the last PDP, they're just the 83/84 CPU
board with a higher clock speed. The 11/93 and /94 are a new
design which uses the J11 CPU. Instead of cache, the entire main
memory (2 or 4 MB) is on-board w/ 70 ns parts. A new memory
controller gate array lets the CPU at the memory during NPR
transfers (even during block mode). A Z80 CPU controls 8 emulated
DL ports (this subsystem is called a DLV22) with buffering, etc.
The board uses the same 18 MHz DCJ11-AE as the 11/8x - all the
speed improvements are from a more modern board design. The 11/9x
will go above 18 MHz.
DEC marketing material:
The PDP-11/94 is the newest and most powerful member of the
PDP-11 family of multiuser systems. The PDP-11/94 features a
new, performance-enhanced processor that combines the DCJ11/FPJ11
chip sets with 2 Mbyte or 4 Mbyte of high-speed onboard memory,
eight buffered, programmable asynchronous serial lines and a time
of year clock. The single-board implementation of the processor
effectively complements the configuration flexibility and
expansion capacity of enhanced UNIBUS systems packaging.
A new performance-enhanced single-board CPU features Digital's
C-MOS 18 MHz J-11 chipset, FPJ-11 coprocessor, parity memory, and
eight buffered serial lines
The full PDP-11 instruction set including floating-point and EIS
instructions, plus an integral floating-point coprocessor
Sophisticated 22-bit memory management, dual register set,
separate instruction and data space, and three system modes:
kernel, supervisor, and user
2 or 4 Mbyte of onboard high-density parity memory
Private Memory Interconnect (PMI) architecture for high-speed
data transfers and enhanced system performance
64 Kbyte bootstrap/diagnostic ROM facility and 8-Kbyte EEPROM
(100% diagnostic coverage)